1. Technical Field
The present invention relates generally to logic circuits for performing arithmetic operations, and more specifically to a method and apparatus for performing rotate operations using cascaded multiplexers.
2. Description of the Related Art
Rotators are used in the arithmetic logic units (ALUs) of microprocessors and are also used in dedicated logic circuits. Rotate operations in graphics applications are efficiently performed using rotators and rotating operations can also be performed in dedicated processing circuits such as parallel-to-serial converters.
High speed rotator circuits using multiplexers are well known in the art. Logarithmic rotators accomplish rotate operations by sequentially performing rotates by fixed powers of 2 in cascaded stages, selecting a rotate or not rotate operation for each stage. By using multiplexers rather than clocked registers, the shift or rotate operations may be performed within a single clock cycle. The time required to complete the operation is set by the propagation delay through the cascaded multiplexer stages.
Logarithmic rotators exhibit a non-uniformity in circuit layout, as the wires that couple the most-significant bits to the inputs of the multiplexers that select the least-significant bits (for a left rotator) are longer and therefore require higher circuit drive levels (e.g., larger transistors). For a right rotator, the same is true for the wires that couple the least-significant bits to the multiplexers that select the most-significant bits are longer.
Additionally, typical logarithmic rotate circuits cannot be used to perform sub-field rotate operations unless circuitry is added to interconnect ends of the sub-fields. Single-instruction-multiple-data (SIMD) instruction sets often include sub-field rotation operations.
Therefore, it would be desirable to provide an improved method and apparatus for performing rotate operations having a uniform, scalable circuit layout.
The objectives of performing rotate operations within a scalable, uniform circuit layout and performing subs field rotations without additional circuitry are achieved in a method and apparatus for performing rotate operations using cascaded multiplexers. Multiple cascaded sets of multiplexer pairs are used to swap bits of an input word provided by an input circuit. A control logic controls the selector inputs of the multiplexer pairs. The control logic has a rotate amount input for controlling whether or not the multiplexer pairs swap bits between bit fields within the input word. An output circuit receives the output of the final multiplexer and the control logic controls the bit field swapping so that the output of the output circuit is a rotated version of the input word, rotated by the rotate amount.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.